共 50 条
- [2] Wafer Edge Defect Study of Temporary Bonded and Thin Wafers in TSV Process Flow 2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2015, : 1707 - 1712
- [3] Electrochemical process for 3D TSV without CMP and lithographic processes Electronic Materials Letters, 2014, 10 : 485 - 490
- [5] TSV Cu Plating and Implications for CMP ELECTRONICS AND 3-D PACKAGING 4, 2011, 33 (36): : 11 - 21
- [6] CMP Process Technology in TSV Application CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2010 (CSTIC 2010), 2010, 27 (01): : 533 - 538
- [7] A Review on the CMP of SiC and Sapphire Wafers ADVANCES IN ABRASIVE TECHNOLOGY XIII, 2010, 126-128 : 429 - 434
- [8] Overcome Challenges in TSV CMP via Slurry Formulation CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2011 (CSTIC 2011), 2011, 34 (01): : 603 - 608
- [9] TSV CMP Process Optimization and Dishing Defect Reduction 2014 INTERNATIONAL CONFERENCE ON PLANARIZATION/CMP TECHNOLOGY (ICPT), 2014, : 99 - 99
- [10] A multiscale mechanical CMP model for patterned wafers THIN FILM MATERIALS, PROCESSES, AND RELIABILITY: PLASMA PROCESSING FOR THE 100 NM NODE AND COPPER INTERCONNECTS WITH LOW-K INTER-LEVEL DIELECTRIC FILMS, 2003, 2003 (13): : 256 - 265