Short-Channel Performance and Mobility Analysis of ⟨110⟩- and ⟨100⟩-Oriented Tri-Gate Nanowire MOSFETs with Raised Source/Drain Extensions

We successfully reduced the parasitic resistance of nanowire transistors (NW Tr.) by raised S/D extensions with thin spacers (<10nm). I-d variations are suppressed by spacer thinning and parasitic capacitance increase is minimal. By adopting < 100 > NW instead of < 110 > NW, I-on = 1mA/mu m for I-off = 100nA/mu m is achieved without stress techniques. Long-L mobility (mu) was systematically studied by separating top and side channel mu. mu of < 100 > nFETs and < 110 > pFETs (potentially-high mu) largely degrade due to side-surface roughness. Gate stress and interface traps affect mu of < 110 > nFETs and < 110 > pFETs, respectively.