New Fault Models and Self-Test Generation for Microprocessors using High-Level Decision Diagrams

被引：2
|
作者：
Jasnetski, Artjom [1 ]
Raik, Jaan [2 ]
Tsertov, Anton [2 ]
Ubar, Raimund [2 ]
机构：
[1] Teston Lab OU, Tallinn, Estonia
[2] Tallinn Univ Technol, Dept Comp Engn, Tallinn, Estonia
来源：
2015 IEEE 18TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS 2015) | 2015年
关键词：
microprocessor; software-based self-test (SBST); test program generation; high-level decision diagrams; FUNCTIONAL TEST-GENERATION;
D O I：
10.1109/DDECS.2015.56
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The paper presents a novel approach to high-level fault modeling and test generation for microprocessors using High-Level Decision Diagrams (HLDD). A general frame-work and novel techniques for automated software-based self-test program generation are discussed. On this basis new previously not published test quality improvement capabilities of the approach are high-lighted and explained. Based on the high level fault model defined for HLDDs a novel class of hard-to-test faults, called "unintended actions", is proposed. In addition, the mechanisms for reducing the risk of fault masking is explained. The experimental results show the superiority of the new method by achieving a higher quality of tests with shorter length compared to the previous results.
引用
收藏
页码：251 / 254
页数：4
相关论文
共 50 条
  • [1] Software-based Self-Test Generation for Microprocessors with High-Level Decision Diagrams
    Ubar, Raimund
    Tsertov, Anton
    Jasnetski, Artjom
    Brik, Marina
    2014 15TH LATIN AMERICAN TEST WORKSHOP - LATW, 2014,
  • [2] Software-based self-test generation for microprocessors with high-level decision diagrams
    Jasnetski, Artjom
    Ubar, Raimund
    Tsertov, Anton
    Brik, Marina
    PROCEEDINGS OF THE ESTONIAN ACADEMY OF SCIENCES, 2014, 63 (01) : 48 - 61
  • [3] High-Level Test Data Generation for Software-Based Self-Test in Microprocessors
    Oyeniran, Adeboye Stephen
    Jasnetski, Artjom
    Tsertov, Anton
    Ubar, Raimund
    2017 6TH MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING (MECO), 2017, : 86 - 91
  • [4] On Automatic Software-Based Self-Test Program Generation Based on High-Level Decision Diagrams
    Jasnetski, Artjom
    Ubar, Raimund
    Tsertov, Anton
    2016 17TH IEEE LATIN-AMERICAN TEST SYMPOSIUM (LATS), 2016, : 177 - 177
  • [5] Diagnostic Modeling of Microprocessors with High-Level Decision Diagrams
    Ubar, R.
    Raik, J.
    Jutman, A.
    Jenihhin, M.
    Brik, M.
    Instenberg, M.
    Wuttke, H-D.
    BEC 2008: 2008 INTERNATIONAL BIENNIAL BALTIC ELECTRONICS CONFERENCE, PROCEEDINGS, 2008, : 147 - 150
  • [6] Synthesis of High-Level Decision Diagrams for Functional Test Pattern Generation
    Ubar, Raimund
    Raik, Jaan
    Karputkin, Anton
    Tombak, Mati
    MIXDES 2009: PROCEEDINGS OF THE 16TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2009, : 519 - +
  • [7] Automated Software-Based Self-Test Generation for Microprocessors
    Jasnetski, Artjom
    Ubar, Raimund
    Tsertov, Anton
    PROCEEDINGS OF THE 24TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS - MIXDES 2017, 2017, : 453 - 458
  • [8] An improved high-level built-in self-test synthesis algorithm
    Yang, LT
    Muzio, J
    ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS, 2001, : 549 - 552
  • [9] High-Level Decision Diagrams based Coverage Metrics for Verification and Test
    Jenihhin, Maksim
    Raik, Jaan
    Chepurov, Anton
    Reinsalu, Uljana
    Ubar, Raimund
    LATW: 2009 10TH LATIN AMERICAN TEST WORKSHOP, 2009, : 49 - 54
  • [10] Multiple Control Fault Testing in Digital Systems with High-Level Decision Diagrams
    Ubar, Raimund
    Oyeniran, Stephen Adeboye
    PROCEEDING OF 2016 IEEE INTERNATIONAL CONFERENCE ON AUTOMATION, QUALITY AND TESTING, ROBOTICS (AQTR), 2016, : 61 - 66
12345