Formal Interpretation of Assertion-Based Features on AMS Designs

被引:8
|
作者
da Costa, Antonio Anastasio Bruto [1 ]
Dasgupta, Pallab [1 ]
机构
[1] Indian Inst Technol, Kharagpur 721302, W Bengal, India
关键词
VERIFICATION;
D O I
10.1109/MDAT.2014.2361720
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The paper proposes the adoption of formal methods for modeling of analog functions. It explains how assertions can be overlaid onto the range of values of individual features in an analog function, and proceeds toward building a mathematical (hybrid automata) model to represent and analyze them. An LDO regulator and a battery charger are used as examples. © 2013 IEEE.
引用
收藏
页码:9 / 17
页数:9
相关论文
共 50 条
  • [1] Practical assertion-based formal verification for SoC designs
    Yeung, Ping
    Larsen, Kenneth
    2005 International Symposium on System-On-Chip, Proceedings, 2005, : 58 - 61
  • [2] Formal Approach to Assertion-Based Code Generation
    Li, Pengyi
    Sun, Jing
    Wang, Hai
    INTERNATIONAL JOURNAL OF SOFTWARE ENGINEERING AND KNOWLEDGE ENGINEERING, 2017, 27 (9-10) : 1637 - 1662
  • [3] Assertion-based debug infrastructure for SoC designs
    Gharehbaghi, Amir Masoud
    Babagoli, Mozhgan
    Hessabi, Shaahin
    2007 INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2007, : 341 - +
  • [4] Multivariant Assertion-Based Guidance in Abstract Interpretation
    Garcia-Contreras, Isabel
    Morales, Jose F.
    Hermenegildo, Manuel, V
    LOGIC-BASED PROGRAM SYNTHESIS AND TRANSFORMATION, LOPSTR 2018, 2019, 11408 : 184 - 201
  • [5] Assertion-Based Verification for System-Level Designs
    Sohofi, Hassan
    Navabi, Zainalabedin
    PROCEEDINGS OF THE FIFTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2014), 2015, : 582 - 588
  • [6] Towards Assertion-Based Verification of Heterogeneous System Designs
    Laemmermann, Stefan
    Ruf, Juergen
    Kropf, Thomas
    Rosenstiel, Wolfgang
    Viehl, Alexander
    Jesser, Alexander
    Hedrich, Lars
    2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010), 2010, : 1171 - 1176
  • [7] AN ASSERTION-BASED VERIFICATION SYSTEM FOR FORMAL REQUIREMENTS DESCRIPTION
    AGUSA, K
    OHNISHI, A
    OHNO, Y
    JAPAN ANNUAL REVIEWS IN ELECTRONICS COMPUTERS & TELECOMMUNICATIONS, 1984, 12 : 11 - 23
  • [8] Automatic assume guarantee analysis for assertion-based formal verification
    Wang, Dong
    Levitt, Jeremy
    ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, : 561 - 566
  • [9] A Dynamic Assertion-Based Verification Platform for Validation of UML Designs
    Banerjee, Ansuman
    Ray, Sayak
    Dasgupta, Pallab
    Chakrabarti, Partha Pratim
    Ramesh, S.
    Ganesan, P. Vignesh V.
    AUTOMATED TECHNOLOGY FOR VERIFICATION AND ANALYSIS, PROCEEDINGS, 2008, 5311 : 222 - 227
  • [10] Automatic UVM Environment Generation for Assertion-based and Functional Verification of SystemC Designs
    Mefenza, Michael
    Yonga, Franck
    Bobda, Christophe
    2014 15TH INTERNATIONAL MICROPROCESSOR TEST AND VERIFICATION WORKSHOP (MTV 2014), 2015, : 16 - 21