Fault injection and simulation for fault tolerant reconfigurable duplex system

被引：0

作者：

Kubalik, Pavel ^{[1
]}

Kvasnicka, Jiri ^{[1
]}

Kubatova, Hana ^{[1
]}

机构：

[1] Czech Tech Univ, Dept Comp Sci & Engn, Karlovo Nam 13, Prague 12135 2, Czech Republic

来源：

PROCEEDINGS OF THE 2007 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS | 2007年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented. Two FPGAs are used for duplex system design, each including the combination of totally self-checking blocks based on parity predictors to obtain better dependability parameters. Combinatorial circuit benchmarks have been considered in all our experiments and computations. A Totally Self-Checking analysis of duplex system is supported by experimental results from our proposed FPGA fault simulator, where SEU-fault resistance is observed. Our proposed hardware fault simulator is compared also with the software simulation. An area overhead of individual parts implemented in each FPGA is also discussed.

引用

页码：357 / +

页数：2

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