On the reconfiguration algorithm for fault-tolerant VLSI arrays

被引：0

作者：

Wu, JG ^{[1
]}

Thambipillai, S ^{[1
]}

机构：

[1] Nanyang Technol Univ, Ctr High Performance Embedded Syst, Singapore 639798, Singapore

来源：

COMPUTATIONAL SCIENCE - ICCS 2003, PT III, PROCEEDINGS | 2003年 / 2659卷

关键词：

degradable VLSI array; reconfiguration; fault-tolerance; greedy algorithm; NP-completeness;

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

In this paper, an improved algorithm is presented for the NP-complete problem of reconfiguring a two-dimensional degradable VLSI array under the row and column routing constraints. The proposed algorithm adopts the partial computing for the logical row exclusion so that the most efficient algorithm, cited in literature, is speeded up without loss of performance. In addition, a flaw in the earlier approach is also addressed. Experimental results show that our algorithm is approximately 50% faster than the above stated algorithm.

引用

页码：360 / 366

页数：7

共 50 条

[1] RECONFIGURATION ALGORITHM OF FAULT-TOLERANT 2-DIMENSIONAL VLSI ARRAYS
KIM, JH
RHEE, P
1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 1989, : 394 - 397
[2] A TAXONOMY OF RECONFIGURATION TECHNIQUES FOR FAULT-TOLERANT PROCESSOR ARRAYS
CHEAN, M
FORTES, JAB
COMPUTER, 1990, 23 (01) : 55 - 69
[3] EFFECTIVE RECONFIGURATION ALGORITHMS IN FAULT-TOLERANT PROCESSOR ARRAYS
BERESFORDSMITH, B
SCHRODER, H
COMPUTING SYSTEMS, 1990, 5 (03): : 169 - 177
[4] A HYPERGRAPH MODEL FOR FAULT-TOLERANT VLSI PROCESSOR ARRAYS
ROSENBERG, AL
IEEE TRANSACTIONS ON COMPUTERS, 1985, 34 (06) : 578 - 584
[5] OPTIMAL MATRIX MULTIPLICATION ON FAULT-TOLERANT VLSI ARRAYS
VARMAN, PJ
RAMAKRISHNAN, IV
IEEE TRANSACTIONS ON COMPUTERS, 1989, 38 (02) : 278 - 283
[6] A comprehensive reconfiguration scheme for fault-tolerant VLSI/WSI array processors
Chen, YY
Upadhyaya, SJ
Cheng, CH
IEEE TRANSACTIONS ON COMPUTERS, 1997, 46 (12) : 1363 - 1371
[7] ON AREA AND YIELD CONSIDERATIONS FOR FAULT-TOLERANT VLSI PROCESSOR ARRAYS
KOREN, I
BREUER, MA
IEEE TRANSACTIONS ON COMPUTERS, 1984, 33 (01) : 21 - 27
[8] HYPERGRAPH MODEL FOR FAULT-TOLERANT VLSI PROCESSOR ARRAYS.
Rosenberg, Arnold L.
IEEE Transactions on Computers, 1985, C-34 (06) : 578 - 584
[9] ARCHITECTURAL FACTORS INFLUENCING THE RELIABILITY OF FAULT-TOLERANT VLSI ARRAYS
BOBBIO, A
MICROELECTRONICS AND RELIABILITY, 1991, 31 (05): : 963 - 968
[10] MINCED TREES, WITH APPLICATIONS TO FAULT-TOLERANT VLSI PROCESSOR ARRAYS
CHUNG, FRK
ROSENBERG, AL
MATHEMATICAL SYSTEMS THEORY, 1986, 19 (01): : 1 - 12

← 1 2 3 4 5 →