Novel method of interconnect worstcase establishment with statistically-based approaches

In order for the interconnect effects due to process-induced variations to be applied to the designs in 0.13 mu m and below, it is necessary to determine and characterize the realistic interconnect worstcase models with high accuracy and speed. This paper proposes new statistically-based approaches to the characterization of realistic interconnect worstcase models which take into account process-induced variations. The Effective Common Geometry (ECG) and Accumulated Maximum Probability (AMP) algorithms have been developed and implemented into the new statistical interconnect worstcase design environment. To verify this statistical interconnect worstcase design environment, the 31-stage ring oscillators are fabricated and measured with UMC 0.13 mu m Logic process. The 15-stage ring oscillators are fabricated and measured with 0.18 mu m standard CMOS process for investigating its flexibility in other technologies. The results show that the relative errors of the new method are less than 1.00%, which is two times more accurate than the conventional worstcase method. Furthermore, the new interconnect worstease design environment improves optimization speed by 29.61-32.01 % compared to that of the conventional worstease optimization. The new statistical interconnect worstcase design environment accurately predicts the worstease and bestcase corners of non-normal distribution where conventional methods cannot do well.