Multiple cell upsets as the key contribution to the total SER of 65 nm CMOS SRAMs and its dependence on well engineering

被引：99
|
作者：
Gasiot, G. [1 ]
Giot, D. [1 ]
Roche, P. [1 ]
机构：
[1] STMicroelect, Cent CAD & Desigh Solut, Front End Technol & Mfg, F-38926 Crolles, France
来源：
IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2007年 / 54卷 / 06期
关键词：
D O I：
10.1109/TNS.2007.908147
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Neutron and alpha SER test results are presented for two SRAMs processed in a commercial 65 nm CMOS technology. Devices with the commonly used triple well option have higher rates of Multiple Cell Upsets (MCU) and therefore higher SER. The same behavior is reported for older technologies from 180 nm to 65 run. Full 3-D device simulations on 65 nm SRAM cells quantify the amplification of the charge collection with the usage of triple well and frequency of well contacts.
引用
收藏
页码：2468 / 2473
页数：6
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