Field Programmable Logic Arrays Implementation of Scene-Based Nonuniformity Correction Algorithm

In this paper, the implementation of scene-based nonuniformity correction (SBNUC) algorithm is presented based on field programmable logic arrays (FPGA) for infrared focal plane arrays (IRFPA). An efficient hardware architecture for the proposed algorithm is presented. The architecture is modeled using C++ in the High-level Synthesis (HLS) tool. Furthermore, it is implemented on an FPGA device fabricated at a 16nm technology node. According to experimental results, low resource utilization, low power consumption, and a maximum frequency of 300MHz are achieved. The simulation and MATLAB results are compared to test the accuracy in which there are close similarities.