RF-MEMS wafer-level packaging using through-wafer interconnect

被引：21
|
作者：
Tian, J. [1 ]
Sosin, S. [1 ]
Iannacci, J. [1 ,2 ]
Gaddi, R. [2 ]
Bartek, M. [1 ]
机构：
[1] Delft Univ Technol, Lab High Frequency Technol & Components DIMES, NL-2628 CD Delft, Netherlands
[2] Univ Bologna, ARCES DEIS, I-40123 Bologna, Italy
来源：
SENSORS AND ACTUATORS A-PHYSICAL | 2008年 / 142卷 / 01期
关键词：
RF-MEMS; Cu plating; through-wafer interconnect; wafer-level packaging;
D O I：
10.1016/j.sna.2007.09.004
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, development of a wafer-level packaging (WLP) process suitable for RF-MEMS applications is presented. The packaging concept is based on a high-resistivity silicon capping substrate that is wafer-level bonded to an RF-MEMS device wafer providing MEMS device protection and vertical electrical signal interconnect. The capping substrate contains Cu-plated through-wafer electrical vias and optional through-substrate cavities allowing for hybrid integration. The RF-MEMS device wafer and the capping substrate are bonded using either solder reflow or an electrically conductive adhesive. After solder bump formation and singulation, this packaging solution results in surface-mount technology compatible components. Moreover, the presented WLP solution allows hybrid integration of additional IC dies that are flip-chip bonded within the capping substrate cavities. (c) 2007 Elsevier B.V. All rights reserved.
引用
收藏
页码：442 / 451
页数：10
相关论文
共 50 条
  • [1] RF-MEMS wafer-level packaging using through-wafer via technology
    Tian, J.
    Iannacci, J.
    Sosin, S.
    Gaddi, R.
    Bartek, M.
    EPTC 2006: 8TH ELECTRONIC PACKAGING TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2006, : 441 - 447
  • [2] Wafer-level packaging of MEMS accelerometers with through-wafer interconnects
    Yun, CH
    Brosnihan, TJ
    Webster, WA
    Villarreal, J
    55TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2005 PROCEEDINGS, 2005, : 320 - 323
  • [3] Reliability study of hermetic wafer level MEMS packaging with through-wafer interconnect
    Sung-Hoon Choa
    Microsystem Technologies, 2009, 15 : 677 - 686
  • [4] Experimental studies of through-wafer copper interconnect in wafer level MEMS packaging
    Choa, Sung-Hoon
    Fracture and Damage Mechanics V, Pts 1 and 2, 2006, 324-325 : 231 - 234
  • [5] Reliability study of hermetic wafer level MEMS packaging with through-wafer interconnect
    Choa, Sung-Hoon
    MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2009, 15 (05): : 677 - 686
  • [6] Parasitic effects reduction for wafer-level packaging of RF-MEMS
    Iannacci, J.
    Tian, J.
    Sinaga, S. M.
    Gaddi, R.
    Gnudi, A.
    Bartek, M.
    DTIP 2006: SYMPOSIUM ON DESIGN,TEST, INTEGRATION AND PACKAGING OF MEMS/MOEMS 2006, 2006, : 25 - +
  • [7] Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections
    Lin, Chiung-Wen
    Yang, Hsueh-An
    Wang, Wei Chung
    Fang, Weileun
    JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 2007, 17 (06) : 1200 - 1205
  • [8] Novel low-loss wafer-level packaging of the RF-MEMS devices
    Park, YK
    Park, HW
    Lee, DJ
    Park, JH
    Song, IS
    Kim, CW
    Song, CM
    Lee, YH
    Kim, CJ
    Ju, BK
    FIFTEENTH IEEE INTERNATIONAL CONFERENCE ON MICRO ELECTRO MECHANICAL SYSTEMS, TECHNICAL DIGEST, 2002, : 681 - 684
  • [9] Electromagnetic optimization of an RF-MEMS wafer-level package
    Iannacci, J.
    Bartek, M.
    Tian, J.
    Gaddi, R.
    Gnudi, A.
    SENSORS AND ACTUATORS A-PHYSICAL, 2008, 142 (01) : 434 - 441
  • [10] Mechanical reliability of silicon wafers with through-wafer vias for wafer-level packaging
    Polyakov, A
    Bartek, M
    Burghartz, JN
    MICROELECTRONICS RELIABILITY, 2002, 42 (9-11) : 1783 - 1788
12345