Harnessing Performance Variability: A HPC-oriented Application Scenario

被引：0

作者：

Massari, Giuseppe ^{[1
]}

Libutti, Simone ^{[1
]}

Portero, Antoni ^{[2
]}

Vavrik, Radim ^{[2
]}

Kuchar, Stepan ^{[2
]}

Vondrak, Vit ^{[2
]}

Borghese, Luca ^{[1
]}

Fornaciari, William ^{[1
]}

机构：

[1] Politecn Milan, DEIB, Milan, Italy

[2] VSB Tech Univ Ostrava, Natl Supercomp Ctr IT4Innovat, Ostrava, Czech Republic

来源：

2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD) | 2015年

关键词：

D O I：

10.1109/DSD.2015.87

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

The technology scaling towards the 10nm of the silicon manufacturing, is going to introduce variability challenges, mainly due to the growing susceptibility to thermal hot-spots and time-dependent variations (aging) in the silicon chip. The consequences are two-fold: a) unpredictable performance; b) unreliable computing resources. The goal of the HARPA project is to enable next-generation embedded and high-performance heterogeneous many-core processors to effectively address this issues, through a cross-layer approach, involving several component of the system stack. Each component acts at different levels and time granularity. This paper focus on one of the components of the HARPA stack, the HARPA-OS, showing early results of a first integration step of the HARPA approach in a real High-Performance Computing (HPC) application scenario.

引用

页码：111 / 116

页数：6

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