Application Of Ti-Based Self-Formation Barrier Layers To Cu Dual-Damascene Interconnects

被引:0
|
作者
Ito, Kazuhiro [1 ]
Ohmori, Kazuyuki [2 ]
Kohama, Kazuyuki [1 ]
Mori, Kenichi [2 ]
Maekawa, Kazuyoshi [2 ]
Asai, Koyu [2 ]
Murakami, Masanori [3 ]
机构
[1] Kyoto Univ, Dept Mat Sci & Engn, Kyoto 6068501, Japan
[2] Renesas Elect Corp, Proc Technol, Hitachinaka, Ibaraki 3128504, Japan
[3] Ritsumeikan Trust, Nakagyo Ku, Kyoto 6048520, Japan
来源
关键词
Cu(Ti) alloy film; self-formation; barrier layer; Cu dual-damascene interconnect; resistivity; reliability; MG ALLOY-FILMS; DIFFUSION; COPPER; RESISTIVITY; TECHNOLOGY; MORPHOLOGY; SIO2;
D O I
暂无
中图分类号
TH [机械、仪表工业];
学科分类号
0802 ;
摘要
Cu interconnects have been used extensively in ULSI devices. However, large resistance-capacitance delay and poor device reliability have been critical issues as the device feature size has reduced to nanometer scale. In order to achieve low resistance and high reliability of Cu interconnects, we have applied a thin Ti-based self-formed barrier (SFB) using Cu(Ti) alloy seed to 45nm-node dual damascene interconnects and evaluated its performance. The line resistance and via resistance decreased significantly, compared with those of conventional Ta/TaN barriers. The stress migration performance was also drastically improved using the SFB process. A performance of time dependent dielectric breakdown revealed superior endurance. These results suggest that the Ti-based SFB process is one of the most promising candidates for advanced Cu interconnects. TEM and X-ray photoelectron spectroscopy observations for characterization of the Ti-based SFB structure were also performed. The Ti-based SFB consisted of mainly amorphous Ti oxides. Amorphous or crystalline Ti compounds such as TiC, TiN, and TiSi formed beneath Cu alloy films, and the formation varied with dielectric.
引用
收藏
页码:91 / +
页数:2
相关论文
共 50 条
  • [1] Performance of Cu Dual-Damascene Interconnects Using a Thin Ti-Based Self-Formed Barrier Layer for 28 nm Node and Beyond
    Ohmori, Kazuyuki
    Mori, Kenichi
    Maekawa, Kazuyoshi
    Kohama, Kazuyuki
    Ito, Kazuhiro
    Ohnishi, Takashi
    Mizuno, Masao
    Asai, Koyu
    Murakami, Masanori
    Miyatake, Hiroshi
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2010, 49 (05) : 05FD011 - 05FD014
  • [2] Effect of annealing ambient on the self-formation mechanism of diffusion barrier layers used in Cu(Ti) interconnects
    Tsukimoto, S.
    Kabe, T.
    Ito, K.
    Murakami, M.
    JOURNAL OF ELECTRONIC MATERIALS, 2007, 36 (03) : 258 - 265
  • [3] Effect of Annealing Ambient on the Self-Formation Mechanism of Diffusion Barrier Layers Used in Cu(Ti) Interconnects
    S. Tsukimoto
    T. Kabe
    K. Ito
    M. Murakami
    Journal of Electronic Materials, 2007, 36 : 258 - 265
  • [4] Length effects on the reliability of dual-damascene Cu interconnects
    Wei, F
    Gan, CL
    Thompson, CV
    Clement, JJ
    Hau-Riege, SP
    Pey, KL
    Choi, WK
    Tay, HL
    Yu, B
    Radhakrishnan, MK
    SILICON MATERIALS-PROCESSING, CHARACTERIZATION AND RELIABILITY, 2002, 716 : 645 - 650
  • [5] Reliability and early failure in Cu/oxide dual-damascene interconnects
    Ogawa, ET
    Lee, KD
    Matsuhashi, H
    Ho, PS
    Blaschke, VA
    Havemann, RH
    JOURNAL OF ELECTRONIC MATERIALS, 2002, 31 (10) : 1052 - 1058
  • [6] Electromigration of lower and upper Cu lines in dual-damascene Cu interconnects
    Krishnamoorthy, A
    Qiang, G
    Vairagar, AV
    Mhaisalkar, S
    MATERIALS, TECHNOLOGY AND RELIABILITY FOR ADVANCED INTERCONNECTS AND LOW-K DIELECTRICS-2003, 2003, 766 : 133 - 138
  • [7] Statistical study for electromigration reliability in dual-damascene Cu interconnects
    Lee, KD
    Ho, PS
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2004, 4 (02) : 237 - 245
  • [8] Electromigration study of Cu/low k dual-damascene interconnects
    Lee, KD
    Lu, X
    Ogawa, ET
    Matsuhashi, H
    Ho, PS
    40TH ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2002, : 322 - 326
  • [9] Reliability and early failure in Cu/oxide dual-damascene interconnects
    Ennis T. Ogawa
    Ki-Don Lee
    Hideki Matsuhashi
    Paul S. Ho
    Volker A. Blaschke
    Robert H. Havemann
    Journal of Electronic Materials, 2002, 31 : 1052 - 1058
  • [10] Effect of via geometry on thermal stress in dual-damascene Cu interconnects
    Chen, L.
    Li, C. J.
    PROCEEDINGS OF THE 2013 20TH IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2013), 2013, : 712 - 715