A Dual-Mode Configurable RF-to-Digital Receiver in 16nm FinFET

被引：0

作者：

Whitcombe, Amv ^{[1
]}

Sheikh, Farhana ^{[2
]}

Alpman, Erkan ^{[2
]}

Ravi, Ashoke ^{[2
]}

Nikolic, Borivoie ^{[1
]}

机构：

[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

[2] Intel Corp, Hillsboro, OR USA

来源：

2018 IEEE SYMPOSIUM ON VLSI CIRCUITS | 2018年

关键词：

RF-to-digital; software-defined radios; FinFET;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A tunable and process-scalable RF-to-digital receiver using a configurable-architecture ADC is implemented in 16nm CMOS. In low-power mode, the 0.7-1.9 GHz receiver is configured as a VCO-based design drawing 9-16 mW and providing -82 dBm sensitivity in a 10 MHz bandwidth. In blocker-tolerant mode, a successive approximation ADC is enabled to obtain an in-band IIP3 of +17 dBm.

引用

页码：23 / 24

页数：2

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