A Parallel Carrier Synchronization Structure For High-speed Communication System

This paper proposes a parallel carrier recovery structure with decision feedback and training pilot to achieve 2.5Gbps communication capacity,which is suitable for high speed demodulator and easy to implement on FPGA platform. Because we can obtain more than one phase detection errors at the same time, classifying and processing multiple phase detection errors can achieve better performance. We present the simulation results of serial floating-point algorithms, parallel fixed-point algorithms with theoretical values at different Eb/N0. Finally, we also performed hardware testing of the algorithm in the laboratory.