Configurable hardware architecture for real-time window-based image processing

被引：0
|
作者：
Torres-Huitzil, C [1 ]
Arias-Estrada, M [1 ]
机构：
[1] INAOE, Dept Comp Sci, Mexico City, DF, Mexico
来源：
FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS | 2003年 / 2778卷
关键词：
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
In this work, a configurable hardware architecture for window-based image operations for real-time applications is presented. The architecture is based on an array of elemental processors under a systolic and pipeline approach to achieve a high rate of processing. A configurable window processor has been developed to cover a broad class of image processing algorithms and operators. The system is modeled in a Hardware Description Language and has been prototyped on an FPGA device. Some implementation and performance results are presented and discussed.
引用
收藏
页码：1008 / 1011
页数：4
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