Optimization analysis of FPGA carry-skip adders for electronics rapid prototyping

The performance study of FPGA (Field Programmable Gate Array) adders' has shown that the carry-skip technique appeares to have the potential to greatly improve the speed of the adders although the results were obtained without considering design optimization. In this work, the timing models for carry-ripple. carry-generate, carry-terminate, and carry-skip are proposed, and an heuristic algorithm is developed to determine the near-optimal configurations of FPGA carry-skip adders. The objective is to minimize the worst-case carry propagation time of FPGA adders and lay some ground work for effective design and development of FPGA-based customized digital circuits and computing systems. The implementation results corroborate reasonably the theoretical analysis and both demonstrate that the speeds of the optimized adders have significantly improved over the carry-ripple adders and the non-optimized adders.