220mV-900mV 794/584/754 Gbps/W Reconfigurable GF(24)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14nm Tri-gate CMOS

A reconfigurable AES/SMS4/Camellia symmetric-key cipher accelerator fabricated in 14nm CMOS achieves 3.17/2.68/3.17 Gbps throughput at 750mV, 25 degrees C. Hybrid GF(2(4))(2) Sbox-based unified datapath with in-line key expansion, polynomial optimization, scaled affine transform assisted multiply-less MixColumns with key-precompute, and shared round constant circuits result in a 9152 mu m(2) design, a 29% area reduction over conventional separate implementations. Look-up-table (LUT) elimination enables sub-threshold operation down to 220mV, with 794/584/754Gbps/W peak energy-efficiency measured at 240mV.