A fast algorithm for transistor folding

被引：6

作者：

Cheng, EYC ^{[1
]}

Sahni, S ^{[1
]}

机构：

[1] Univ Florida, Dept Comp & Informat Sci & Engn, Gainesville, FL 32611 USA

来源：

VLSI DESIGN | 2001年 / 12卷 / 01期

关键词：

transistor folding; row-based design; area minimization; complexity;

D O I：

10.1155/2001/96353

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Transistor folding reduces the area of row-based designs that employ transistors of different size. Kim and Kang [1] have developed an O(m(2) log m) algorithm to optimally fold m transistor pairs. In this paper we develop an O(m(2)) algorithm for optimal transistor folding. Our experiments indicate that our algorithm runs 3 to 60 times as fast for m values in the range (100, 100,000).

引用

页码：53 / 60

页数：8

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