A 0.6-V 10-bit 200-kS/s SAR ADC With Higher Side-Reset-and-Set Switching Scheme and Hybrid CAP-MOS DAC

This paper presents a low-power and area efficient 10-bit SAR ADC with higher side-reset-and-set (HSRS) switching scheme and hybrid capacitive-MOS (CAP-MOS) DAC. The HSRS switching scheme consumes zero switching energy for the two most-significant bits and skips unnecessary switching without using any auxiliary circuit. It is further verified in this paper that the HSRS switching scheme shows lower nonlinearity compared with the conventional CDAC structure with the same unit capacitor size and matching condition. This additional advantage permits using DAC topologies with lower total capacitance under given linearity requirement. A hybrid CAP-MOS DAC is adopted to reduce the total capacitance of the DAC, which consumes lower static current and chip area than the conventional hybrid capacitive-resistive DAC under the same settling requirement. The prototype 10-bit SAR ADC is implemented in a 0.18-mu m CMOS technology, showing an SNDR/SFDR of 56.43 dB/71 dB at 90-kHz input, under a 0.6-V power supply, while consuming 1.01 mu W at 200 kS/s for a figure of merit of 9.32 fJ/conv.-step. The ADC occupies only a small active area of 0.0675 mm(2).