Closed-Form Modeling Approach of Trap-Assisted Tunneling Current for Use in Compact TFET Models

This paper presents a novel compact modeling approach to consider the effect of trap-assisted tunneling (TAT) in the calculations of the tunneling current in tunnel field-effect transistors (TFETs). The closed-form and physics-based model equations are implemented in the hardware description language Verilog-A and thus extend an existing model for the B2B tunneling current calculation in double-gate (DG) TFETs. In order to verify the modeling approach, simulation results are compared to TCAD Sentaurus simulations. The compact model shows a good fit in the current transfer curves for various drain-source voltages, trap densities, drain doping concentrations and different source materials. The current output curve and the output conductance stay also in good agreement with TCAD data. In the next step, the compact model is verified with the help of measurements of fabricated complementary TFET devices. During the verification process, limitations and advantages of the modeling approach are analyzed and discussed. The influence of TAT on a fabricated single-stage TFET inverter is investigated in a last verification step, whereby the numerical stability and flexibility of the model is demonstrated.