A 7.6 mW, 214-fs RMS Jitter 10-GHz Phase-Locked Loop for 40-Gb/s Serial Link Transmitter Based on Two-Stage Ring Oscillator in 65-nm CMOS

被引：0

作者：

Bae, Woorham ^{[1
]}

Ju, Haram ^{[1
]}

Park, Kwanseo ^{[1
]}

Cho, Sung-Yong ^{[1
]}

Jeong, Deog-Kyoon ^{[1
]}

机构：

[1] Seoul Natl Univ, Dept Elect & Comp Engn, Interuniv Semicond Res Ctr, Seoul, South Korea

来源：

2015 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) | 2015年

关键词：

2-stage ring oscillator; jitter; phase-locked loop;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a -245.3 dB FoM(J) phase-locked loop based on a ring oscillator and a novel analysis on 2-stage ring oscillator. The proposed PLL generates a 4-phase 10-GHz clock for a 40-Gb/s serial link transmitter. The proposed analysis offers a time-domain insight on 2-stage ring oscillator and a precise prediction on oscillator behavior such as an output frequency and whether the 2-stage ring oscillates or not, based on a simple open-loop approach with a single stage buffer. The prototype chip is fabricated in 65-nm CMOS technology, and the PLL occupies only 0.009 mm(2) and dissipates 7.6 mW from 1.2-V supply and 9 mW from 1.3-V supply. The measured integrated jitter of the PLL is 214 fs from 1.2-V supply and 182 fs from 1.3-V supply, which corresponds to -244.6 dB and -245.3 dB FoM(J), respectively.

引用

页码：165 / 168

页数：4