An approach to modeling and testing memories and its application to CAMs

被引：16

作者：

Sidorowicz, PR ^{[1
]}

Brzozowski, JA ^{[1
]}

机构：

[1] Univ Waterloo, Dept Comp Sci, Waterloo, ON N2L 3G1, Canada

来源：

16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/VTEST.1998.670899

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An approach to modeling and testing memories is presented and illustrated using an n-word by l-bit (n x l) static content-addressable memory (CAM) array for cell input stuck-at faults. An input stuck-at fault model for a CAM is defined, and a test of length 7n + 2l + 5 with 100% fault coverage with respect to this fault model is constructed. This test also detects all the usual cell stuck-at and transition faults. Finally, some design-for-testability (DFT) modifications facilitating a further reduction of this test's length are proposed.

引用

页码：411 / 416

页数：6

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