SLOPE SENSING FOR OPTIMUM DYNAMIC GATE DRIVING OF SIC POWER MOSFETS

To suppress excessive gate voltage swings during switching, a resistance is normally used to limit the charging rate of the gate capacitance (C-G). Modern solutions, such as segmented gate drivers, can be used to dynamically control the gate resistance R-G to minimize ringing while maintaining the fast-switching speed of the transistor. The timing or dynamic pattern of the gate resistance is critical in the optimization of the device and circuit performance. Traditionally, this gate drive pattern is obtained via a trial-and-error or iterative procedure. This paper proposes a method to automatically determine the timing intervals by monitoring the gate signal (V-GATE) through slope sensing with analog filter and subsequent mixed-signal processing. The output timing indicator (T-SEG) is then fed back to the segmented gate driver IC to achieve automatic adjustments of the dynamic driving pattern. The proposed system is able to determine the optimum T-SEG for dynamic gate driving. For the SiC power MOSFET used in our testing, segmented R-G driving between 2.5 and 10 Omega does not hinder the switching speed, while keeping the undershoot of the SiC module to be within 1 V or 5% of the total applied gate voltage.