Multiple-Loop Design Technique for High-Performance Low-Dropout Regulator

A new multiple-loop design technique for high-performance low-dropout (LDO) regulator designs has been proposed and successfully implemented in many commercial products for portable smart phone and tablet PC applications. The proposed LDO is composed of five loops that allows designers to obtain a good tradeoff between quiescent current and other performances, such as undershoot, overshoot, and so on. A total of one bandgap reference and 38 LDOs (including n-type and p-type LDOs, which will be named NLDO and PLDO, respectively) were integrated in one power-management IC chip for powering an application processor inside mobile devices. The proposed LDO has been fabricated based on 0.13-mu m CMOS process and supplies various current capacities from 50 to 600 mA; 38 LDOs have been designed and supply different output voltage levels from 0.7 to 3.0 V. One of the proposed NLDOs consumes 14 mu A of the quiescent current and features under 56/24 mV of undershoot/overshoot at VOUT = 1V as the load current steps up from 0 to 300 mA with 300 mA/1 mu s on a 1-mu F output capacitor. The measured output load and line regulations are 1.8 and 0.4 mV, respectively. The measured integrated output noise from 10 Hz to 100 kHz at I-LOAD = 10% of maximum current shows 80 mu Vrms. The package chip size is 6.25x6.25 mm(2) with 169 balls.