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- [1] A VHDL generation tool for optimized parallel FIR filters IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP, 2006, : 134 - +
- [2] VHDL Generation of Optimized FIR Filters SCS: 2008 2ND INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS, 2008, : 424 - +
- [4] A VHDL based functional compiler for optimum architecture generation of FIR filters ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4, 1996, : 564 - 567
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- [7] A CAD tool for the automatic generation of synthesizable parallel prefix adders in VHDL MICROELECTRONICS: DESIGN, TECHNOLOGY, AND PACKAGING III, 2008, 6798
- [8] An evolutionary approach to automatic generation of VHDL code for low-power digital filters GENETIC PROGRAMMING, PROCEEDINGS, 2001, 2038 : 36 - 50
- [9] AUTOMATIC VHDL GENERATION SOFTWARE TOOL FOR PARAMETERIZED FPGA BASED FFT ARCHITECTURES PROCEEDINGS OF THE IEEE 2010 NATIONAL AEROSPACE AND ELECTRONICS CONFERENCE (NAECON), 2010, : 306 - 309
- [10] High Level Testability Analysis using VHDL Automatic Test Pattern Generation 2008 IEEE MEDITERRANEAN ELECTROTECHNICAL CONFERENCE, VOLS 1 AND 2, 2008, : 204 - 209