Analog circuit for synapse neural networks VLSI implementation

被引：0
|
作者：
Chible, H [1 ]
机构：
[1] Lebanese Univ, Beirut, Lebanon
来源：
ICECS 2000: 7TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS & SYSTEMS, VOLS I AND II | 2000年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
In this paper, I present an analog VLSI circuit to implement the synapse operation in the artificial neural network systems. This circuit is a two-quadrant (or four-quadrant) analog multiplier. The output of the synapse circuit is in current and it is proportional to the multiplication of two input voltages: the weight voltage and the pattern information input voltage (or the output voltage of the neuron). The main feature of the multiplier is the high value of the weight voltage range, which it varies between the ground voltage and the supply voltage [0:Vdd].
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页码：1004 / 1007
页数：4
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