An Efficient Block-Based Architecture for Reconfigurable FIR Filter Using Partial-Product Method

Multipliers are the most demanding component of any filter. They not only dominate most of the chip area but also contribute to most of the computational delay. An efficient realization of filter thus requires optimization of the multipliers. In this paper, a high performance block reconfigurable finite impulse response filter structure is presented. Block-based realization improves the overall throughput of the structure. A novel partial-product-based structure is proposed for Multiply and Accumulation operation, instead of traditional multipliers-based structure. Pipelining and parallelism in the structure improves the throughput of the design. The reuse of the partial products reduces the number of adders and increases the speed, thereby reducing the area-delay product (ADP) and energy-per output (EPO), in comparison with the earlier reported structures. The comparative analysis is done with the help of ASIC synthesis results and the results show that the proposed architecture for filter order 16 and block input 8requires 28.91% less ADP and 25.72% less EPO than the earlier reported architecture.