A new Schmitt trigger circuit in a 0.13-μm 1/2.5-V CMOS process to receive 3.3-V input signals

被引：36
|
作者：
Chen, SL [1 ]
Ker, MD [1 ]
机构：
[1] Natl Chiao Tung Univ, Nanoelect & Gigascale Syst Lab, Inst Elect, Hsinchu 300, Taiwan
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2005年 / 52卷 / 07期
关键词：
gate-oxide reliability; input-output (I/O); mixed-voltage interface; Schmitt trigger;
D O I：
10.1109/TCSII.2005.850409
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new Schmitt trigger circuit, which is implemented by low-voltage devices to receive the high-voltage input signals without gate-oxide reliability problem, is proposed. The new proposed circuit, which can be operated in a 3.3-V signal environment without suffering high-voltage gate-oxide overstress, has been fabricated in a 0.13-mu m 1/2.5-V 1P8M CMOS process. The experimental results have confirmed that the measured transition threshold voltages of the new proposed Schmitt trigger circuit are about 1 and 2.5 V, respectively. The new proposed Schmitt trigger circuit is suitable for mixed-voltage input-output interfaces to receive input signals and reject input noise.
引用
收藏
页码：361 / 365
页数：5
相关论文
共 30 条
  • [1] A new Schmitt trigger circuit in a 0.13 μm 1/2.5 V CMOS process to receive 3.3 V input signals
    Chen, SL
    Ker, MD
    2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 573 - 576
  • [2] An output buffer for 3.3-V applications in a 0.13-μm 1/2.5-V CMOS process
    Chen, Shih-Lun
    Ker, Ming-Dou
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2007, 54 (01) : 14 - 18
  • [3] A new output buffer for 3.3-V PCI-X application in a 0.13-μm 1/2.5-V
    Chen, SL
    Ker, MD
    PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004, : 112 - 115
  • [4] An Enhanced Well-Changed GGNMOS for 3.3-V ESD Protection in 0.13-μm SOI Process
    Zhou, Mo
    Shan, Yi
    Dong, Yemin
    IEICE TRANSACTIONS ON ELECTRONICS, 2020, E103C (06) : 332 - 334
  • [5] Level shifters for high-speed 1-v to 3.3-v interfaces in a 0.13-μm Cu-Interconnection/Low-k CMOS technology
    Wang, WT
    Ker, MD
    Chiang, MC
    Chen, CH
    2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS, 2001, : 307 - 310
  • [6] Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
    Ker, Ming-Dou
    Chen, Wen-Yi
    Hsu, Kuo-Chun
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2006, 53 (10) : 2187 - 2193
  • [7] Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
    Ker, MD
    Chen, WY
    Hsu, KC
    2005 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 43RD ANNUAL, 2005, : 606 - 607
  • [8] A 2.5-V,1-Gb/s/ch parallel optical receiver in 0.25μm CMOS technology
    Jung, SJ
    Kim, HS
    Kim, DG
    Choi, YW
    OPTOELECTRONIC INTERGRATED CIRCUITS AND PACKAGING V, 2001, 4290 : 52 - 61
  • [9] A 1-V, 82-dB, 2.5-MS/s, single loop, single bit delta-sigma modulator in 0.13-μm CMOS technology
    Tao, Yonghong
    Yao, Libin
    Lian, Yong
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2012, 71 (02) : 171 - 178
  • [10] A 1-V, 82-dB, 2.5-MS/s, single loop, single bit delta-sigma modulator in 0.13-μm CMOS technology
    Yonghong Tao
    Libin Yao
    Yong Lian
    Analog Integrated Circuits and Signal Processing, 2012, 71 : 171 - 178
123