Self-timed pipelining using latest arriving signal detection

A self-timed pipelining methodology using latest arriving signal detection is presented. The self-timing control block in the algorithm consists of a self-timing signal generator and pipelining latches. The computation completion of a logic block can be detected and the data latched by the pulse-type self-timing signal for further processing. Using the algorithm, a 32-bit carry lookahead adder is implemented. Simulation results show that the adder can operate at 800MHz in 0.25 mum CMOS technology.