Design of An Approximate FFT Processor Based on Approximate Complex Multipliers

The Fast Fourier Transform (FFT) is an efficient algorithm to calculate the Discrete Fourier Transform (DFT), which is often employed in Digital Signal Processing (DSP) and communication. In FFT, complex multiplication and addition units in the butterfly module consume most of the hardware resources. Compared to the addition operation, multiplication is more complicated. In this paper, the multiplier in the complex multiplication unit of the FFT is approximated. Four Radix-4 Booth multipliers with different approximation levels are proposed to reduce the hardware complexity. The pipeline HT and the parallel FFT based on the proposed approximate multipliers are implemented and extensively evaluated. Compared with the state-of-the-art FFT designs, the LUTs amount is reduced up to 20.3% and 29.1% for pipeline and parallel FFTs, respectively. The power is reduced up to 69.9% for pipeline FFT, and the delay is reduced up to 45.7%. Moreover, the PSNR is reduced by less than 1dB in both pipeline FFT and parallel EFT. Proved by experiment results, the overall performance of the proposed designs is better than FIT designs using other approximate multipliers.