An application of the second-order passive lead-lag loop filter for analog PLLs to the third-order charge-pump PLLs

被引：8
|
作者：
Yao, Chia-Yu [1 ]
Yeh, Chin-Chih [2 ]
机构：
[1] Natl Taiwan Univ Sci & Technol, Dept Elect Engn, Taipei 106, Taiwan
[2] Huafan Univ, Dept Elect Engn, Taipei 223, Taiwan
来源：
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS | 2008年 / 55卷 / 02期
关键词：
charge-pump phase-locked loops (CPPLLs); frequency synthesizers; passive loop filters;
D O I：
10.1109/TIE.2007.909082
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
A second-order passive lead-lag loop filter for analog phase-locked loop (PLLs) is modified in this paper for the third-order charge-pump PLLs (CPPLLs). The analysis shows that the CPPLL employing the modified loop filter results in smaller area, lower power consumption, or better noise performance than the CPPLL employing the conventional loop filter.
引用
收藏
页码：972 / 974
页数：3
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