A 86 MHz-12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS

被引：47

作者：

Borremans, Jonathan ^{[1
]}

Vengattaramane, Kameswaran ^{[1
]}

Giannini, Vito ^{[1
]}

Debaillie, Bjoern ^{[1
]}

Van Thillo, Wim ^{[1
]}

Craninckx, Jan ^{[1
]}

机构：

[1] IMEC, B-3001 Louvain, Belgium

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2010年 / 45卷 / 10期

关键词：

Background calibration; CMOS; DAC; digital-intensive; digital phase modulation; digital-to-analog converter; fractional-N; PLL; TDC; time-to-digital converter; 40; nm; RING OSCILLATOR; 90-NM CMOS; BAND VCO; CONVERTER; RECEIVER; NOISE; TRANSMITTER; PATH;

D O I：

10.1109/JSSC.2010.2063630

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 86 MHz-12 GHz digital-intensive reconfigurable PLL frequency synthesizer is presented with 100 kHz to 2 MHz bandwidth. It leverages a 6 fJ/ step 5.5 ps, 14b coarse-fine TDC and a 6-12 GHz dual-VCO set. Several simple calibration schemes are proposed that enable the proper performance of the highly efficient TDC in the PLL. The 0.28 mm(2) synthesizer, which is appropriate for use in a Software-Defined Radio, features Delta Sigma noise cancellation and digital phase modulation and consumes less than 30 mW.

引用

页码：2116 / 2129

页数：14

共 11 条

[1] A 6fJ/step, 5.5ps Time-to-Digital Converter for a Digital PLL in 40nm Digital LP CMOS
Borremans, J.
Vengattarmane, K.
Craninckx, J.
2010 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS RFIC SYMPOSIUM, 2010, : 417 - 420
[2] An 800-MHz-6-GHz software-defined wireless receiver in 90-nm CMOS
Bagheri, Rahim
Mirzaei, Ahmad
Chehrazi, Saeed
Heidari, Mohammad E.
Lee, Minjae
Mikhemar, Mohyee
Tang, Wai
Abidi, Asad A.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (12) : 2860 - 2876
[3] A 100MHz-2GHz Wireless Receiver in 40-nm CMOS for Software-Defined Radio
Peng, Y.
Liu, Y.
Yang, F.
Zhang, X. L.
Yu, X. P.
Lu, Z. H.
Lim, W. M.
2011 INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2011,
[4] A 0.1-5GHz Dual-VCO Software-Defined ΣΔ Frequency Synthesizer in 45nm Digital CMOS
Nuzzo, Pierluigi
Vengattaramane, Kameswaran
Ingels, Mark
Giannini, Vito
Steyaert, Michiel
Craninckx, Jan
RFIC: 2009 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM, 2009, : 287 - +
[5] A 2-mm2 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS
Giannini, Vito
Nuzzo, Pierluigi
Soens, Charlotte
Vengattaramane, Kameswaran
Ryckaert, Julien
Goffioul, Michael
Debaillie, Bjorn
Borremans, Jonathan
Van Driessche, Joris
Craninckx, Jan
Ingels, Mark
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (12) : 3486 - 3498
[6] A 50 MHz-6 GHz, 2 x 2 MIMO, Reconfigurable Architecture, Software-Defined Radio in 130nm CMOS
Analui, Behnam
Mercer, Timothy
Mandegaran, Sam
Goel, Ankush
Hashemi, Hossein
2014 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM, 2014, : 329 - 332
[7] A 64-fJ/Conv.-Step Continuous-Time ΣΔ Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital ΔΣ Truncator
Tsai, Hung-Chieh
Lo, Chi-Lun
Ho, Chen-Yen
Lin, Yu-Hsin
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (11) : 2637 - 2648
[8] A 28fJ/conv-step CT ΔΣ Modulator with 78dB DR and 18MHz BW in 28nm CMOS Using a Highly Digital Multibit Quantizer
Shu, Yun-Shiang
Tsai, Jui-Yuan
Chen, Ping
Lo, Tien-Yu
Chiu, Pao-Cheng
2013 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2013, 56 : 268 - +
[9] A 65-nm CMOS 1 GS/s 45 mW Hybrid Digital-to-Analog Converter (DAC) With Digital Deglitch Mechanism Achieving 13.83 fJ/step FOM for 5G New Radio Sub-6 GHz Applications
Idros, Norhamizah
Rajendran, Jagadheswaran
Mariappan, Selvakumar
Li, Yizhi
Wang, Shengquan
Rhaffor, Nuha
Kumar, Narendra
Alghaihab, Abdullah
Nathan, Arokia
Yarman, Binboga Siddik
IEEE ACCESS, 2024, 12 : 170596 - 170609
[10] A 0.5V 1.6mW 2.4GHz Fractional-N All-Digital PLL for Bluetooth LE with PVT-Insensitive TDC using Switched-Capacitor Doubler in 28nm CMOS
Kuo, Feng-Wei
Pourmousavian, Seyednaser
Siriburanon, Teerachot
Chen, Ron
Cho, Lan-chou
Jou, Chewn-Pu
Hsueh, Fu-Lung
Staszewski, Robert Bogdan
2017 SYMPOSIUM ON VLSI CIRCUITS, 2017, : C178 - C179

← 1 2 →