Verification coverage: when is enough, enough?

被引：1

|

作者：

Bacchini, Francine ^{[1
]}

Hu, Alan J. ^{[2
]}

Fitzpatrick, Tom ^{[3
]}

Lacey, David ^{[4
]}

Piziali, Andrew ^{[5
]}

Ranjan, Rajeev ^{[6
]}

Tan, Mercedes ^{[7
]}

Ziv, Avi ^{[8
]}

机构：

[1] Francine Bacchini Inc, San Jose, CA USA

[2] Univ British Columbia, Vancouver, BC, Canada

[3] Mentor Graph Corp, San Jose, CA USA

[4] Hewlett Packard Corp, Richardson, TX USA

[5] Cadence Design Syst, Parker, TX USA

[6] Jasper Design Automat, Mountain View, CA USA

[7] Sun Microsyst, Sunnyvale, CA USA

[8] IBM Corp, Haifa, Israel

来源：

2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2007年

关键词：

design verification; verification test plan; functional simulation; formal verification; coverage;

D O I：

10.1109/DAC.2007.375262

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

引用

收藏

页码：744 / +

页数：2

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