Appropriate wafer preparation for thickness uniformity of PACE-processed SOI wafers

For bonded SOI wafers with active silicon layers thinner than 1 mu m, controlling thickness uniformity of active layers has been developed recently. A Plasma Assisted Chemical Etching (PACE) technology is one of methods to realize 0.1 mu m bonded SOI. When this technology was proposed for the first time, it was believed that 0.1 mu m thick bonded SOI wafers were easily produced independent of initial SOI layer thickness prior to the PACE process. It was true to create 0.1 mu m SOI thickness in average. However, the uniformity appeared to be dependent on initial SOI material as well as the PACE machine capability itself. Tile SOI thickness uniformity pattern after PACE looked like surface morphology of polished silicon wafers. Thus, for each polishing process In bonded SOI fabrication, we applied various polishing methods and found appropriate wafer polishing methods for the better thickness uniformity of PACE processed SOI wafers.