Fast Spiking Neural Network architecture for low-cost FPGA devices

Spiking Neural Networks (SNN) consist of fully interconnected computation units (neurons) based on spike processing. This type of networks resembles those found in biological systems studied by neuroscientists. This paper shows a hardware implementation for SNN. First, SNN require the inputs to be spikes, being necessary a conversion system (encoding) from digital values into spikes. For travelling spikes, each neuron interconnection is characterized by weights and delays, requiring an internal neuron processing by a Postsynaptic Potential (PSP) function and membrane potential threshold evaluation for a post-synaptic output spike generation. In order to model a real biological system by artificial SNN, the number of required neurons is very high (thousands). In this work, we propose a SNN architecture able to adapt big size networks using reduced hardware resources. While spikes are processed at 1ms time, inter spike time is used for internal calculations, a mixed serial-parallel structure allows optimized computation of all neuron output values. Results show that SNN can be accommodated using a medium-size FPGA device such as Xilinx Spartan 3 with processing speed comparable to fully parallel implementations with up to 70% resource reduction.