Si-Nanowire TAHOS (TaN/Al2O3/HfO2/SiO2/Si) Nonvolatile Memory cell

被引:1
|
作者
Fu, J. [1 ]
Singh, N. [1 ]
Yang, B. [1 ]
Zhu, C. X. [1 ]
Lo, G. Q. [1 ]
Kwong, D. L. [1 ]
机构
[1] ASTAR, Inst Microelect, Singapore 117685, Singapore
关键词
D O I
10.1109/ESSDERC.2008.4681712
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Silicon nanowire based discrete trapped charge-storage nonvolatile memory cell employing high-kappa dielectrics with metal gate is presented for the first time. The nanowire TAHOS (TaN/Al2O3/HfO2/SiO2/Si) memory fabricated using top-down method in nearly gate-all-around (GAA) architecture showed higher P/E speed than SONOS. In TAHOS, the erase speed is found almost equal to the program speed. The improvements are attributed to the reduced electrical oxide thickness (EOT) of the dielectric layers, increased electric field in tunnel oxide, deep trap levels in the HfO2 charge trapping layer, and suppression of gate electron injection by Al2O3 blocking layer. The fabricated nanowire TAHOS devices also exhibit large window after ten year of retention, achieving a better trade-off between long retention and fast program/erase property.
引用
收藏
页码:115 / 118
页数:4
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