Interconnect issues post 45nm

被引：0

作者：

Rossnagel, SM ^{[1
]}

Wisnieff, R ^{[1
]}

Edelstein, D ^{[1
]}

Kuan, TS ^{[1
]}

机构：

[1] IBM Corp, Div Res, Yorktown Hts, NY 10598 USA

来源：

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Despite many projections on the inevitable post-PVD evolution of interconnect technology, it remains PVD-based for liner-seed through 45 nm and perhaps farther, with an ALD process change the obvious next step perhaps followed by a switch from Ta to Ru.. Cu size effects are not critical to low-level (1x) line RC and the biggest performance opportunity is with the high level fat lines. CA technology; both barrier and fill, does not scale well and may evolve to more interconnect-like materials, potentially unifying two tooling areas.

引用

页码：95 / 97

页数：3

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