Design of an SFQ Full Adder as a Single-Stage Gate

被引：2

作者：

Cong, Haolin ^{[1
]}

Katam, Naveen Kumar ^{[1
]}

Pedram, Massoud ^{[1
]}

机构：

[1] Univ Southern Calif, Dept Elect & Comp Engn, Los Angeles, CA 90007 USA

来源：

2019 IEEE INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) | 2019年

关键词：

RSFQ; full adder; single-stage complex gate;

D O I：

10.1109/isec46533.2019.8990964

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the design of a one-bit full adder with sum and carry outputs as two single-stage gates, which could save the JJ count and the area compared with the conventional design of a full-adder. The schematics of both the Sum and Carry cells are shown in this paper along with their input and output waveforms of JSIM simulations in the time domain. The circuit cost is compared between the conventional full adder and the new single-stage adder design in terms of the area and the time. Integer dividers of several sizes are synthesized with conventional full-adder and the proposed single-stage adder to illustrate the advantages of the new design.

引用

页数：3

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