A folded VLSI architecture of decision feedback equalizer for QAM modem

被引:0
|
作者
Yu, H [1 ]
Kim, BW [1 ]
Cho, JD [1 ]
机构
[1] Sungkyunkwan Univ, Sch Informat & Commun, Suwon 440746, South Korea
关键词
decision feedback equalizer; QAM; VLSI; FIR filter; folding;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, an area efficient VLSI architecture of decision feedback equalizer is derived accommodating 64/256QAM modulators. This architecture is implemented efficiently in VLSI structure using EDA tools due to its regular structure. The method is to employ a time-multiplexed design scheme, so-called Folding, which executes multiple operation on a single functional unit [12]. In addition, we define a new folding set by grouping the adjacent filter taps with data transfer having the same processing sequence between blocks and perform the internal data-bit optimization. By doing so, the computational complexity is reduced by performance optimization and also silicon area is reduced by using a shared operator. Moreover, through the performance and convergence time comparison of the various LMS (e.g. LMS, data signed LMS, error signed LMS, signed-signed LMS)) coefficient updating algorithms, we identify an optimum LMS algorithm scheme suitable for the low complexity, high performance and high order (64 and 256) QAM applications for the presented Fractionally Spaced Decision Feedback Equalizer. We simulated the proposed design scheme using SYNOPSYS(TM) and SPW(TM).
引用
收藏
页码:628 / 639
页数:12
相关论文
共 50 条
  • [1] Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modem
    Yu, HS
    Kim, BW
    Cho, YG
    Cho, JD
    Kim, JW
    Lee, JK
    Park, HC
    Lee, KW
    PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 2001, : 404 - 407
  • [2] High-performance VLSI architecture of decision feedback equalizer for gigabit systems
    Lin, Chih-Hsiu
    Wu, An-Yeu
    Li, Fan-Min
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2006, 53 (09) : 911 - 915
  • [3] An Efficient VLSI Architecture for Computing Decision Feedback Equalizer Coefficients from the Channel State Information
    Thomas Sailer
    Gerhard Tröster
    Journal of VLSI signal processing systems for signal, image and video technology, 2003, 35 : 91 - 103
  • [4] An Energy Efficient VLSI Architecture of Decision Feedback Equalizer for 5G Communication System
    Khan, Mohd Tasleem
    Shaik, Rafi Ahamed
    IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 2017, 7 (04) : 569 - 581
  • [5] An efficient VLSI architecture for computing decision feedback equalizer coefficients from the channel state information
    Sailer, T
    Tröster, G
    JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2003, 35 (01): : 91 - 103
  • [6] Soft-threshold-based multilayer decision feedback equalizer (STM-DFE) algorithm and VLSI architecture
    Lin, CH
    Wu, AY
    IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2005, 53 (08) : 3325 - 3336
  • [7] A blind decision feedback equalizer for QAM signals based on the constant modulus algorithm
    Beasley, Antoinette
    Cole-Rhodes, Arlene
    MILCOM 2006, VOLS 1-7, 2006, : 500 - +
  • [8] A low power normalized-LMS decision feedback equalizer for a wireless packet modem
    Garrett, D
    Nicol, C
    Blanksby, A
    Howland, C
    ISLPED'02: PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2002, : 290 - 294
  • [9] High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme
    Yang, MD
    Wu, AY
    Lai, JT
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (02) : 218 - 226
  • [10] TROPOSCATTER TEST-RESULTS FOR A HIGH-SPEED DECISION-FEEDBACK EQUALIZER MODEM
    EHRMAN, L
    MONSEN, P
    IEEE TRANSACTIONS ON COMMUNICATIONS, 1977, 25 (12) : 1499 - 1504