Low Power CMOS Inverter in Nanometer Technology

Nowadays, the Leakage power is one of the major issue for CMOS circuit on nanometer technology. And it is increases as the process technology become finer and finer with device density increases. As the supply voltage lower down, gate oxide thickness have to reduce to reduce the threshold voltage which helps in maintaining the performance. But there is significant increase in leakage power dissipation as the threshold voltage decreases. So, in this paper we are studying different technique of leakage power reduction and suggested a proposed technique to reduce leakage power dissipation. The proposed technique is the combination of the existing Leakage reduction techniques (LECTOR) and body biasing of its leakage control transistor. The proposed technique reduced the static power of CMOS Inverter by 9.13% and 17.21% for input voltage 0 and 1 respectively as compared to standard LECTOR technique and also reduces the delay causes because of LCTs in dynamic mode to some extent maintaining the performance of circuit. All the circuit designing and simulation has been done on CADENCE virtuoso in 45nm technology.