Implementation issues for congestion control in ATM networks

The design of Broadband Integrated Services Digital Networks (B-ISDN) requires the investigation of specific techniques to guarantee different Quality of Services (QoS) requirements for each traffic class in the network. In this context, a unified environment for the simulation and design of an ATM node is a useful approach to test the effectiveness and the implementation aspects of the techniques mentioned above. In this paper a complete ATM node has been modelled in VHDL in a modular and flexible way and critical computational aspects are investigated.