A Java']Java processor architecture with bytecode folding and dynamic scheduling

被引：0
|
作者：
El-Kharashi, MW [1 ]
Elguibaly, F [1 ]
Li, KF [1 ]
机构：
[1] Univ Victoria, Dept Elect & Comp Engn, Victoria, BC, Canada
来源：
2001 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING, VOLS I AND II, CONFERENCE PROCEEDINGS | 2001年
关键词：
!text type='Java']Java[!/text] virtual machine; !text type='Java']Java[!/text] processors; !text type='Java']Java[!/text] bytecode folding; reservation stations; Tomasulo's algorithm;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a novel processor architecture for executing Java bytecodes in hardware. Our processor is based on an instruction folding algorithm implemented with Tomasulo's scheduling algorithm. The architecture also provides dual processing capability to execute Java bytecodes as well as other binaries. This approach improves Java execution without sacrificing the generality of the processor.
引用
收藏
页码：307 / 310
页数：4
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