A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations

被引：0

作者：

Marella, Sravan K. ^{[1
]}

Kumar, Sanjay V. ^{[1
]}

Sapatnekar, Sachin S. ^{[1
]}

机构：

[1] Univ Minnesota, Dept Elect & Comp Engn, Minneapolis, MN 55455 USA

来源：

2012 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) | 2012年

关键词：

3D IC; Through Silicon Via; Static Timing Analysis; Finite Element Method; TEMPERATURE-DEPENDENCE; RELIABILITY; IMPACT;

D O I：

暂无

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

In 3D ICs, TSV-induced thermal residual stress impacts transistor mobilities due to the piezoresistive effect. This phenomenon is coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. In this paper, analytical models are developed to holistically represent the effect of thermally-induced variations on circuit timing. The analysis is based on a semianalytic formulation that is demonstrated to accurately capture the biaxial nature of TSV stress and its effect on delay.

引用

页码：317 / 324

页数：8

共 33 条

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