RETRACTED: A new compaction strategy for enhancing the utilization of reconfigurable chips (Retracted article. See vol. 80, pg. 719, 2015)

Field programmable gate arrays (FPGAs) are designed to implement any logic circuit with the ability to host several independent tasks simultaneously. They inherit reconfigurability from their programmable architecture. However, designs are usually dynamic and the arrival times of tasks may be unknown in advance. Accordingly, FPGA should have the ability to: (1) place incoming tasks at run time, and (2) compact the chip whenever needed. Compaction is a proposed solution to alleviate external fragmentations. It tries to move running tasks closer to each others to free a sufficient area for hosting more tasks. Unfortunately, traditional compaction techniques suffer from internal and external fragmentations. This paper introduces a novel puzzle-based compaction (PBC) technique. PBC is a shape-aware technique that is the first to take the task shape into consideration. Hence, it succeeds not only to eliminate the internal fragmentations but also to minimize the external fragmentations. Moreover, the paper develops a novel formula, which is the first not to estimate, but to exactly calculate the amount of external fragmentations generated by hosting a set of tasks inside the reconfigurable chip. Experimental results have shown that PBC outperforms recent compaction techniques in which the chip utilization has reached 87 %.