Embedded Low Power Clock Generator for Sensor Nodes

In this paper an embedded clock generation solution for low power sensor nodes is presented. A design example of a Digitally Controlled Oscillator (DCO) is given and compared to other approaches. The paper discusses the most common clock architectures for sensor nodes, their design challenges and potential integration issues. The proposed DCO is adjustable to 64 different frequencies in the range of 5 : 8 MHz to 1 3 : 9 MHz fed by a 2 : 5 V voltage supply. With an area utilization of 0 : 0 2 4 mm(2) in a 0 : 2 5 mu m SiGe BiCMOS process, and an average current consumption of less than 1 0 6 mu A, it fits best into power-area trade off for an internal several-MHz clock generator. It is designed as an IP-Core and can be placed directly into the digital core of a sensor node. Due to its robustness, the DCO can be connected to the noisy digital voltage supply. A test chip was sent to fabrication.