A Technique to Reduce Transition Energy for Fault Tolerant Data Bus in DSM Technology

Energy dissipation of interconnects is becoming a bottle neck for high performance integrated circuits. This energy dissipation is due to increase in inter-wire capacitance. As CMOS VLSI integration continues with shrinking feature size, the energy dissipation on the on-chip data buses and long capacitance also increases. This capacitance on on-chip data buses and long interconnects plays an important role in the reliability and performance of the system. These on-chip data buses consumes major portion of wiring energy. To increase the reliability and performance of the system it is necessary to reduce the energy dissipation on the data bus. Hence transition energy reduction data bus encoding scheme is proposed which can reduce the energy dissipation on on-chip data buses. The proposed technique can able to reduce the energy dissipation by 32% to 40% for 12-bit, 21-bit, 38-bit and 71-bit data buses compare with unencoded data and 1% to 31% more compare with other existing techniques. (C) 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of C3IT