BonnPlace: Placement of leading-edge chips by advanced combinatorial algorithms

被引：22
|
作者：
Brenner, Ulrich [1 ]
Struzyna, Markus [1 ]
Vygen, Jens [1 ]
机构：
[1] Univ Bonn, Res Inst Discrete Math, D-53113 Bonn, Germany
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2008年 / 27卷 / 09期
基金：
新加坡国家研究基金会;
关键词：
layout; network flows; physical design; placement; quadratic optimization;
D O I：
10.1109/TCAD.2008.927674
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
BonnPlace is the placement tool of the University of Bonn, Germany. It is continuously used in the industry for the placement of most complex chips. Global placement is based on quadratic placement and multisection. Legalization of macros and standard cells uses minimum cost flow and dynamic programming algorithms. We describe details of our implementation and present new experimental results.
引用
收藏
页码：1607 / 1620
页数：14
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