A hardware accelerator for IEEE 802.15.4 Time-Slotted Channel Hopping transceiver

Time-Slotted Channel Hopping (TSCH), an operational mode of the IEEE 802.15.4e standard, imposes a high workload on the embedded processor, mainly due to its precise timing. The limited embedded processor of an edge device cannot satisfy the considerable memory footprint and computational complexity caused by functions that need precise timing in the protocol stack. Moving such duties to hardware seems to be a viable path towards offloading the processor and releasing its resource to be used for running firmware related to the implementation of the upper layers of the protocol stack as well as the application. In this work, a TSCH protocol hardware accelerator is designed and integrated within the digital baseband processor of an IEEE 802.15.4 transceiver. The whole system is implemented targeting the TSMC 65 nm technology. The designed TSCH accelerator has an efficient interface and is totally configurable by the software. It efficiently controls the transceiver, frees up embedded processor cycles, and reduces the interrupt callback to the processor. Therefore, the TSCH hardware accelerator makes it possible to use a cheaper embedded processor or to operate the processor on a lower clock speed which results in lower power consumption. The power analysis of the implemented system shows that, in the minimal setting of the TSCH accelerator, only 0.1% is added to the power consumption of the digital baseband processor. The power overhead increases to 5.6% for supporting three parallel slotframes which is a widely used TSCH setting in multi-hop networks. In return, the embedded processor is relaxed of processing TSCH timing related interrupts that are required for software-based TSCH implementation.