A New Three-Phase Inverter Topology for Reducing the dv/dt and Peak-to-Peak Value of Common Mode Voltage

Existing dc and ac bypass-assisted two-level three-phi inverter topologies can only reduce the peak-to-peak (P-to-P) common mode voltage (CMV) value by 66.6%. However, the dv/dt of CMV remains unchanged. This issue can be easily addressed by using a multilevel inverter but it increases the size, cost, and complexity of the system. As an alternative, this article proposes a novel three-phase inverter topology where one leg (out of three) of the inverter is configured to produce three-level pole voltage while the other two legs produce two-level pole voltages. This results in a unique space vector (SV) diagram with 12 SVs, whereas a 2-level inverter has only 8 SVs. A new pulsewidth modulation scheme is proposed that can utilize the SV diagram in such a way that dv/dt of CMV is reduced by 50% along with a 66.6% reduction in CMV P-to-P value in each switching cycle. Another advantage of the proposed topology is the reduced conduction losses due to fewer switches conducting at any given time. The proposed topology is compared with the existing solutions to prove its advantages. Simulation and experimental results are presented for a three-phase induction motor load to validate the various claims.