A High-Power SOI-CMOS PA Module with Fan-Out Wafer-Level Packaging for 2.4 GHz Wi-Fi 6 Applications

被引：2
|
作者：
Reynier, P. [1 ]
Serhan, A. [1 ]
Parat, D. [1 ]
Mourot, R. [1 ]
Gaye, M. [2 ]
Kauv, P. [2 ]
Cardoso, A. [3 ]
Gouvea, A. [3 ]
Nogueira, S. [3 ]
Giry, A. [1 ]
机构：
[1] CEA, LETI, MINATEC Campus, F-38054 Grenoble, France
[2] Keysight Technol, Les Ulis, France
[3] Amkor Technol Inc, Porto, Portugal
来源：
2021 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC) | 2021年
关键词：
CMOS; FOWLP; Power Amplifier; SOI; Wi-Fi; 6;
D O I：
10.1109/RFIC51843.2021.9490483
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents the first high-power SOI-CMOS power amplifier (PA) embedded in a Fan-Out Wafer Level Package (FOWLP) and addressing 2.4 GHz Wi-Fi 6 applications. At 2.44 GHz, the PA delivers 35.1 dBm of saturated output power (P-sat) with 53% of peak PAE and 29.5 dB of power gain. Without DPD, the PA achieves state-of-the art measured performance with 26.5/24.5/21.9 dBm of linear output power ( Pout) for an EVM (Error Vector Magnitude) of -30/-35/-43 dB with an operating current of 336/270/210 mA for MCS7/9/11 40MHz signals respectively. The PA shows robust operation under extreme load mismatch (8: 1 VSWR) and temperature (-40 to 80 degrees C) conditions.
引用
收藏
页码：59 / 62
页数：4
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